The present invention generally relates to methods of producing a semiconductor device, and more particularly to a method of producing a semiconductor device having an element such as a bipolar transistor with a silicon on insulator (SOI) structure using a wafer bonding technique.
The SOI structure using the wager bonding technique was proposed back in the 1960's. A semiconductor device having the so-called dielectric isolation structure is also known, where the dielectric isolation structure is obtained by forming on a dielectric substrate a thin silicon layer which is made by etching back a monocrystalline silicon (Si) substrate.
Recently, many attempts have been made to combine such structures to produce a semiconductor device having a high quality. But when producing such a semiconductor device, the formation of the high impurity concentration buried layer plays an important role.
FIGS. 1A through 1E are cross sectional views for explaining a conventional method of producing a semiconductor device having the SOI structure. Such a conventional method is disclosed in the Japanese Laid-Open Patent Application No. 58-9334, for example.
In FIG. 1A, an n-type silicon (Si) wafer 1 having a thickness of 300 microns is prepared and an n.sup.+ -type diffusion layer 2 is formed in the n-type Si wafer 1 to a thickness of approximately 20 microns. The n.sup.+ -type diffusion layer 2 has a resistivity in a range of several to several tens of m.OMEGA.cm. Hence, a low-resistivity buried layer is formed in advance.
In FIG. 1B, an anodized layer 3 is formed in the n.sup.+ -type diffusion layer 2 to a thickness of approximately 10 microns by an anodization.
In FIG. 1C, an adhesive layer 5 is formed on a semiconductor wafer 4 which is used as a base substrate, and the anodized layer 3 is bonded on the semiconductor wafer 4 through the adhesive layer 5. A pressure of approximately 200 g/cm.sup.2 is applied on the pair of wafers 1 and 4 and the stacked structure is heated for approximately 3 minutes at approximately 100.degree. C. Thereafter, the stacked structure is subjected to a thermal process for several tens of minutes at 1000.degree. C. so as to evaporate an organic component of the adhesive layer 5. As a result, a combined wafer 6 is made including the wafers 1 and 4 which are bonded together by the adhesive layer 5.
In FIG. 1D, a photoresist layer (not shown) is formed on the semiconductor wafer 4 and approximately 260 microns of the n-type Si wafer 1 is removed by an etching using an etchant including hydrofluoric acid (HF), nitric acid (HNO.sub.3) and acetic acid (CH.sub.3 COOH) with a ratio 1:3:1. As a result, an n-type region 1a of approximately 20 microns remains on the N.sup.+ -type diffusion layer 2.
In FIG 1E, an SiO.sub.2 insulator layer 11 is formed on the n-type region 1a, and windows (not shown) are formed in the SiO.sub.2 insulator layer 11 for forming a p-type region 8 by an ion implantation through the SiO.sub.2 insulator layer 11. Thereafter, an N.sup.+ -type region 9 is formed in the p-type region 8 and an N.sup.+ -type region 10 is formed in the n-type region 1a by an ion implantation through holes formed in the SiO.sub.2 insulator layer 11. As a result, elements 7a, 7b and 7c are formed in the n-type region 1a. Each of the elements 7a through 7c have the p-type region 8 which becomes a base region of an npn bipolar transistor, the N.sup.+ -type region 9 which becomes an emitter region of the npn bipolar transistor and the N.sup.+ -type region 10 which is used for forming a portion of a collector electrode of the npn bipolar transistor. Finally, a base electrode, an emitter electrode and a collector electrode (all not shown) are formed at respective holes in the SiO.sub.2 insulator layer 11 located above the p-type region 8, the N.sup.+ -type region 9 and the N.sup.+ -type region 10.
However, when removing a portion of the n-type Si wafer 1 by the etching which uses the etchant including HF, HNO.sub.3 and CH.sub.3 COOH, it is extremely difficult to carry out the etching so that the thickness of the n-type region 1a is controlled with a high accuracy. As a result, there is a problem in that the thickness of the n-type region 1a remaining on the N.sup.+ -type diffusion layer 2 is inconsistent because the etching of the n-type wafer 1 cannot be controlled with a high accuracy. When the thickness of the n-type region 1a is inconsistent, there is a problem in that the inconsistency in the characteristics of the elements formed in the n-type region 1a becomes large since the n-type region 1a is used as an active region in which the elements of the semiconductor device are formed. Therefore, it is impossible to produce semiconductor devices having desired element characteristics with a high yield.